使用雜訊移頻逐次逼近暫存技術之 2+1 SMASH 調變器的設計與實現

Abstract

類比數位轉換器(ADC)是一個將類比訊號轉換成數位訊號的裝置，在各種電子應用中至關重要。ADC的應用範圍極廣，從音頻處理到數據通訊、感測器信號處理，再到醫療器材等領域，效能通常以解析度和取樣率來衡量，解析度代表它能夠區分的細節程度，而取樣率則是它每秒能夠處理的樣本數。三角積分調變器(Delta Sigma Modulation)是一種熱門的ADC，利用超取樣和雜訊移頻技術來實現高解析度，其核心概念是利用超取樣來提升訊號的解析度，同時通過雜訊移頻將雜訊從訊號頻帶內移至高頻部分。這種特性使DSM在處理小信號和高精度要求的應用中具有優勢。它常見於音頻設備、精密儀器、通信系統以及其他需要高解析度和低雜訊的應用中。本文介紹了一種操作在1.7V電壓下的離散時間CIFB2+1雜訊移頻逐次逼近式類比數位轉換器。通過採用SMASH架構來解決單一迴路在實施高階時所面臨的穩定性問題，該轉換器有效地消除了雜訊並提高了性能。此外，我們提出了一種新穎的雙階段量化技術來提高線性度，通過減少參考電壓之間的差異，實現了比預期更佳的解析度，這種設計有效地避免對於訊號擺幅增大時面臨的非線性問題。該電路使用NS SAR ADC進行量化，並對上一次DAC電容切換後的殘留電壓進行運算，以降低比較器雜訊、DAC的settling error和mismatch對電路效能的影響。所呈現的三角積分調變器採用0.18-μm CMOS製程技術製造。基於20-kHz頻寬和7 MHz取樣頻率，晶片量測結果下，SNDR達到76.1 dB，而在1.7V的供應電壓下功耗為267μW，Schreier figure-of-merit(FoMs)為157.6dB。An Analog-to-Digital Converter (ADC) is a device that converts analog signals into digital signals, playing a crucial role in various electronic applications. The applications of ADCs are extensive, ranging from audio processing to data communications, sensor signal processing, and medical instruments. The performance of an ADC is typically measured in terms of resolution and sampling rate, where resolution represents the level of detail it can distinguish, and sampling rate is the number of samples it can process per second. Delta Sigma Modulation (DSM) is a popular type of ADC that achieves high resolution by utilizing oversampling and noise shaping techniques. The core concept of DSM is to enhance signal resolution through oversampling while pushing the noise out of the signal band to higher frequencies via noise shaping. This feature makes DSM advantageous in applications requiring the handling of small signals and high precision. It is commonly used in audio equipment, precision instruments, communication systems, and other applications that demand high resolution and low noise.This paper introduces a discrete-time CIFB 2+1 noise-shaping successive approximation register (SAR) ADC operating at a voltage of 1.7V. By adopting the SMASH architecture, this converter effectively addresses the stability issues faced by single-loop implementations at higher orders, thereby eliminating noise and enhancing performance. Furthermore, we propose a novel two-stage quantization technique to improve linearity by reducing the difference between reference voltages, achieving better-than-expected resolution. This design effectively avoids nonlinearity issues encountered with increased signal swing.The circuit uses an NS SAR ADC for quantization and processes the residue voltage after the previous DAC capacitor switching to mitigate the impact of comparator noise, DAC settling errors, and mismatches on the circuit's performance. The presented DSM is fabricated using 0.18-μm CMOS technology.In a circuit implementation based on a 20-kHz bandwidth and a 7 MHz sampling frequency, the Signal-to-Noise and Distortion Ratio (SNDR) reaches 76.1 dB, with a power consumption of 267 μW at a supply voltage of 1.7V. The Schreier figure-of-merit (FoMs) is 157.6 dB.