記憶體之3D立體控制單元與高介電常數之矽鍺電晶體

Abstract

電子產品朝向輕薄短小、高效能發展已成趨勢，高度的系統整合將無可避免；具體積小、整合度高、耗電量低、成本低等特性的立體堆疊晶片（3D IC）將成趨勢。 第二章節的目的在單晶片矽上利用連續成長製程完成適用於 3D 記憶體之switch技術評估與試製，並輔以 TCAD 模擬配合，以利於最佳化設計。在製程驗證方面，目前垂直型多晶矽 p-n diode switch 完成驗證的電性表現，如理想因子 (ideal factor) η約1.2~1.9，電流密度(J)在1.8V時約1.5x102 A/cm2，且 on/off ratio 也達到 ~107 ，已可供記憶體switch使用。 而為能適用於雙極性記憶體 (如RRAM) 的使用，則因其寫入及抹除屬不同極性，故需發展雙向型控制單元，類似雙極性載子電晶體 (BJT) 之n/p/n或p/n/p結構，第三章節考慮採用n/p/n接面之雙極性二極體 ( bi-directional diode )。 第四章研究架方向為氮化鈦 (TiN) 金屬閘極搭配 HfSiOx介電層在不同晶格方向 (crystal orientation) 之N型場效電晶體 (FET) 元件之製作。並以臨界電壓 (threshold voltage, VT) 、次臨界擺幅 (subthreshold swing, S.S.) 、飽和電流 (saturation current, IDsat) 、漏電流 (leakage current) 等作為元件特性評估之依據。

Now the compact and high-performance electronic products are world-widely used in our life. The integration of system is significant for novel electronics. The trend of electronics is the 3D stack integration circuit (3D IC) which has a lot of advantage: compact, low power, low cost, and high compatibility for CMOS process. In chapter 2, the switch devices of 3D IC were fabricated by a continuous process on single-crystal silicon wafers. In order to improve the design of device, we used TCAD simulation for optimizing results of the device. In the experiments, the electrical characterization and measurement results of vertical poly-Si p-n diode switch are almost equal to the results of simulation, and the ideal factor η is 1.2~1.9 of this device. When the device is biased at 1.8 V, the current density is 1.5x102 A/cm2, and the on/ off ratio reaches ~107. In chapter 3, in order to improve the compatibility with the bi-polar memory device (ex: RRAM), the n/ p/ n junctions bi-directional diode is used as a bi-direction control unit. In chapter 4, we fabricated the NFETs with metal gate (TiN) and the high-k dielectric layer (HfSiOx) in the different crystal orientations. Therefore, the threshold voltage VT, sub-threshold swing S.S, saturation current IDsat, and the leakage current were measured totally for the characterization of the above NFETs.