應用於5G行動通訊之28GHz與38GHz相移器設計

Abstract

本論文實現兩顆應用於Ka頻段的五位元相移器設計，第一顆相移器採用標準0.18-μm 1P6M互補式金屬氧化物半導體製程來實現，整體晶片面積(包含PAD)為0.94 mm × 0.57 mm，操作頻率在27 GHz至29 GHz，180°相移器使用相位可反向衰減器(PIVA)架構，90°相移器使用反射式相移器(RTPS)架構，剩餘位元皆為開關式相移器(STPS)架構。整體輸入反射係數小於 -14.13 dB、輸出反射係數小於 -5.35 dB，中心頻28GHz時，RMS振幅誤差為0.15 dB、RMS相位誤差為3.77°、直流功率消耗為0 mW。 第二顆相移器採用標準65-nm 1P9M互補式金屬氧化物半導體製程來實現，整體晶片面積(包含PAD)為0.67 mm × 0.49 mm，操作頻率為36 GHz至40 GHz，架構與第一顆同，180°相移器使用相位可反向衰減器架構，90°相移器使用反射式相移器架構，剩餘位元皆為開關式相移器架構。整體輸入反射係數小於 -13.03 dB、輸出反射係數小於 -8.09 dB，中心頻38GHz時，RMS振幅誤差為0.82 dB、RMS相位誤差為0.83°、直流功率消耗為0 mW。

Two Ka-band 5-bits phase shifters have been designed and presented in this thesis. The first phase shifter was fabricated on standard 0.18-μm 1P6M CMOS process and designed from 27 GHz to 29 GHz. The proposed phase shifter consists of a phase-invertible variable attenuator (PIVA), a reflection type phase shifter (RTPS), and switch type phase shifters (STPS) which provides 360° phase shifts with the resolution of 11.25°. The measured input return loss is better than 14.13 dB and the output return loss is better than 5.35 dB. The RMS amplitude error is 0.15 dB and the RMS phase error is 3.77° at 28GHz. The chip size is 0.94 mm × 0.57 mm and the dc power consumption is zero. The second phase shifter was fabricated on standard 65-nm 1P9M CMOS process and designed at 36 GHz to 40 GHz. The proposed phase shifter consists of a phase-invertible variable attenuator (PIVA), a reflection type phase shifter (RTPS), and switch type phase shifters (STPS) which provides 360° phase shifts with the resolution of 11.25°. The measured input return loss is better than 13.03 dB and the output return loss is better than 8.09 dB. The RMS amplitude error is 0.82 dB and the RMS phase error is 0.83° at 38GHz. The chip size is 0.67 mm × 0.49 mm and the dc power consumption is zero.