低功率鎖相迴路與電壓控制振盪器之設計與實現

Abstract

隨著無線通訊產業蓬勃發展，高速率傳輸資料是必需的。然而在無線通訊系統中需要穩定且乾淨的振盪源。因此鎖相迴路是相當重要的角色。本論文使用了TSMC CMOS 0.18-µm製程實現可操作在5.568 GHz頻段上的鎖相迴路以及使用TSMC CMOS 90-nm製程實現在K-band頻段上的變壓器回授之電壓控制振盪器。在這次設計操作在5.568 GHz頻段上的鎖相迴路過程中，我們使用低功耗的真單向相位時脈(True Single Phase Clock, TSPC)與低電壓操作的變壓器回授之電壓控制振盪器來達到節省功耗之效果。 本論文依序說明了應用於K-Band低功耗CMOS變壓器回授之電壓控制振盪器與鎖相迴路，分別在第三章與第四章呈現。在第三章實現出了一個低電壓且操作在K頻段上的電壓控制振盪器，其功率消耗為1 mW。其相位雜訊為-95.37 dBc/Hz @ 1 MHz。第四章設計了一個操作在5GHz頻段上的鎖相迴路，整體的功率消耗約為9.23 mW，其相位雜訊為-106.23 dBc/Hz @ 1 MHz與-121.63 dBc/Hz @ 10 MHz。

With the rapid growth of wireless communication system, the high speed data-rate is required. For wireless communication applications, a stable and clean local oscillator is required. Therefore, phase-locked loop is a key component in wireless transceiver. In addition, due to the limitation of battery capacity for handheld device, the low-power is an important design issue. In this thesis, a low power phase-locked loop and a K-band low power CMOS transformer-feedback voltage control oscillator are presented by using TSMC CMOS 0.18-µm and 90-nm process, respectively. This thesis implements a K-band transformer-feedback voltage controlled oscillator and phase-locked loop in chapter 3 and chapter 4, respectively. The K-band transformer-feedback voltage controlled oscillator is presented in chapter 3. The power consumption and the phase noise of the frequency synthesizer are 1 mW and -95.37 dBc/Hz at 1 MHz offset, respectively. In chapter 4, a 5.568 GHz phase-locked loop is presented, which power consumption is 9.23 mW and measured phase noise is -106.23 dBc/Hz at 1 MHz offset.