具有時序交錯且取樣率為200MS/s之無時脈10位元逐次逼近暫存式類比數位轉換器

Abstract

在近年來，因半導體技術的快速發展、科技產品的推陳出新，行動通訊裝置日益普及。隨著行動通訊裝置的需求越來越高，高效能且低功耗的通訊裝置成為電路設計的主流。除了價錢和實用性外，對於便利性和品質更是講究。因此，在眾多的類比數位轉換器架構中，逐次逼近式類比數位轉換器(Successive Approximation Register ADC, SAR ADC)最符合本研究所需要的條件。其架構簡單，只需要一個比較器即可完成類比數位轉換，是目前最省電的架構。此外，由於製程技術逐年提升，在高速類比數位轉換器中，SAR ADC也開始嶄露頭角。

本論文提出一個無需時脈產生器的逐次逼近式類比數位轉換器，其ADC只需觸發一有效信號即可使內部自行產生所需之時脈信號。此架構運用了時序交錯的技術，除了取樣率等效於兩倍外，兩個SAR ADC僅需透過一控制電路即可使取樣和比較階段進行交替。本研究是採用TSMC 90nm 1P9M CMOS製程，在供應電源為1.2V和等校取樣率為200MHz的模擬下，所得到的信號雜訊比為58.94dB，INL和DNL分別為0.734/-0.552及0.735/-0.404，總消耗功率為4.9mW，品質因數為33.7-fJ/conversion-step。

In recent years, mobile communication devices are more popular due to the rapid development of semiconductor technology and the innovation of technology products. Nowadays, the mainstream products trends are high-performance and low-power mobile communication devices. In addition to price and practicality, the mobile communication devices are more convenient and quality. Therefore, in all of analog-to-digital converter (ADC) types, successive approximation analog-to-digital converter (SAR ADC) is appropriate for this research design. It is the most power-efficient architecture since its simple structure using only one comparator which is needed to complete whole sampling data during each conversion phase. Besides, in high-speed analog-to-digital converters, SAR ADC can be implemented with the advanced process.

In the thesis, a clock-free 200-MS/s 10-bit time-interleaved (TI) successive approximation register analog-to-digital converter is proposed. The presented SAR ADC can generate required clock by itself while an active signal is asserted. In the presented TI structure, two SAR ADCs are alternated with entering sample and comparison phases by the control circuit, and thus the equivalent sample rate can be doubled. The presented ADC is simulated under TSMC 90nm 1P9M CMOS process. Under a supply voltage of 1.2-V and an equivalent sampling rate of 200-MS/s, the resulted SNDR of the proposed ADC is 58.94 dB, which is equivalent to the ENOB of 9.50-bit. The simulated DNL and INL are within 0.735 / -0.404 and 0.734 / -0.552, respectively. The total power consumption of 4.9 mW and the figure of merit(FOM) is 33.7-fJ/conversion-step。