極低寄生電容之靜電放電防護設計

Abstract

本篇論文研究主軸為極低寄生電容之全晶片靜電放電防護設計，採用0.18-μm之CMOS以及SiGe BiCMOS製程，並實際搭配所設計的靜電放電防護元件應用至不同頻段的低雜訊放大器。

在CMOS製程設計堆疊式二極體內嵌入式矽控整流器，該元件有小的佈局面積、低寄生電容、以及高耐受度。將堆疊式二極體內嵌入式矽控整流器應用至操作在24-GHz的低雜訊放大器，並驗證全晶片靜電放電防護設計。使用BiCMOS製程設計垂直式NPN元件，降低元件的觸發電壓，並將垂直式NPN元件加在2.4-GHz低雜訊放大器上模擬電路特性。

The main thesis of this dissertation is a whole-chip electrostatic discharge (ESD) protection design with ultra-low parasitic, and the ESD devices are applied to radio-frequency integrated circuit (RFIC). The ESD devices are attached to low-noise amplifier (LNA) at 2.4-GHz and 24-GHz in 0.18-μm SiGe BiCMOS and CMOS technologies, respectively. The stacked diodes with embedded silicon-controlled rectifier (SDeSCR) is designed in 0.18-μm CMOS technology, which has advantages of small layout area, low parasitic capacitance, and strong ESD robustness. In addition, the SDeSCR devices are applied to the 24-GHz LNA, and the function of the LNA with SDeSCR devices is verified. The VNPN device is fabricated in 0.18-μm SiGe BiCMOS technology. The proposed design effectively reduces the trigger voltage of the VNPN device. The characteristics of 2.4-GHz LNA with VNPN devices are simulated.