應用於 X 頻段之鎖相迴路與頻率合成器之設計與實現

Abstract

隨著通訊產業發展蓬勃，在講求高資料傳輸速率的時代，許多應用已經都被發展到高頻段上，然而在這些高頻段應用的通訊系統皆需要一個穩定且純淨的振盪源，因此，鎖相迴路扮演了一個關鍵的角色。本論文使用了TSMC CMOS 0.18-µm 製程實現可操作在 X 頻段上的鎖相迴路與頻率合成器。在這次設計的過程中，我們使用電流再利用技術與變壓器回授型態的壓控振盪器來達到節省功耗之效果。 本論文依序實現了壓控振盪器、除頻器、鎖相迴路與頻率合成器，分別在第三章、第四章、第五章與第六章呈現。四個電路主要都是設計在 X 頻段上。第五章設計了一個操作在 X 頻段上的鎖相迴路，整體的功率消耗約為 38 mW，其相位雜訊為-94 dBc/Hz @ 1 MHz。在第六章整合了第三章、第四章與第五章實現出了一個低電壓且操作在 X 頻段上的頻率合成器，並且具有一組 2bits 的控制線，可切換三個頻道，其功率消耗為 36.76 mW。相位雜訊在 In-band 為-75 dBc/Hz @ 100 kHz 且在 out-band 為-120 dBc/Hz @ 10 MHz。With the rapid growth of communication system, the demand for high data-rate is required. Many applications have been developed to high frequency band for broad spectrum. However, the communication for applications in high band require source oscillator which are stable and pure. Therefore, phase-locked loop plays a critical role. In this thesis, a phase-locked loop and a frequency synthesizer in X-band are presented by using TSMC CMOS 0.18-µm process. This thesis implement a voltage controlled oscillator, divider, phase-locked loop and frequency synthesizer in chapter 3, chapter 4, chapter 5 and chapter 6, respectively. The four work main design in X-band. In chapter 5, a X-band phase-locked loop is presented, which power consumption is 38 mW and measured phase noise is -94 dBc/Hz at 1 MHz offset. The frequency synthesizer with a 2 bits control line is presented in chapter 6. The power consumption and the phase noise of the frequency synthesizer are 36.76 mW and -75 dBc/Hz at 100 KHz offset, respectively.