應用於負電壓電路之高耐壓靜電放電防護設計

Abstract

隨著製程日益進步，電晶體的閘極氧化層相較過往更加脆弱，靜電放電測試對電路的可靠度評估已成為重要指標。而在一些高壓電路應用中，必須更加慎重考慮靜電放電對電路的影響。閘極氧化層隨著製程越來越薄，供應電壓也會隨之降低，故使用低壓元件來達到高耐壓特性成為一大挑戰。此外，相較於一般只使用正電壓供應的電路，一些如植入式生醫電路、發電廠自動裝置等，通常會配置正、負電壓源。先前許多論文使用低壓元件來達到可承受高電壓的箝位電路，並已證實其有效性，但幾乎僅針對正電壓下的防護設計，對於負電壓下的箝位電路研究非常稀少。並且在負電壓工作下，共接地的p型基底會有超乎預期的寄生路徑，因此在設計電路時必須多加考量，以避免電路的不當操作。第二章提出了應用在負電壓下之高耐壓靜電放電箝位電路，所有電路均在TSMC 0.18-μm 1.8V/3.3V CMOS製程下實現。為了解決上述寄生路徑的問題，整個箝位電路除了在最高電位使用pMOS外，其餘部分使用nMOS，並利用深層n型井隔開共接地p型基底與nMOS的p型井，且深層n型井接至最高電位(0V)。此外，由於低壓元件的閘極氧化層較薄，故設計電路時每個電晶體的任兩端跨壓最高只能承受1×VDD，如此可解決閘極氧化層可靠度的問題。第三章對提出的電路做各種量測，包含分析其耐受度以及長時間可靠度在室溫以及嚴苛環境下的變化，來驗證提出的電路能有效的保護內部電路。第四章總結所述，本論文提出了高耐壓靜電放電箝位電路，並針對面積以及導通效率進行最佳化，分別提出了兩種不同的電路。經量測驗證，提出的箝位電路在不影響電路正常工作下，能有效解決電路在負電壓電源線間的靜電放電問題。With the development of process, the gate-oxide of the transistor has become more vulnerable than in the past, and electrostatic discharge testing has become an important indicator for evaluating the reliability of circuits. In some high-voltage circuit applications, it is necessary to consider carefully the impact of electrostatic discharge on the circuit. As the gate-oxide layer becomes thinner in the process, the supply voltage decreases accordingly. Therefore, using low-voltage components to achieve high-voltage-tolerant characteristics becomes a major challenge. In addition, comparing to circuits that only use positive voltage supply, some applications such as implantable biomedical circuits, power plant automatic devices typically require both positive and negative voltage sources. Some previous papers have used low-voltage devices to achieve high-voltage-tolerant clamp circuit, and prove the effectiveness. However, research on clamp circuit under negative voltage is rare. Moreover, under normal circuit operation with negative voltage, the common-grounded P-substrate can exhibit unexpected parasitic paths, necessitating careful circuit design to avoid improper operation.Chapter 2 proposes a high-voltage-tolerant ESD clamp circuit under negative voltage, and all circuits have been fabricated in TSMC 0.18-μm 1.8V/3.3V CMOS process. To address the issue of parasitic paths, the entire clamp circuit uses pMOS at the highest voltage level, with the rest using nMOS. A deep n-well (DNW) is used to separate the p-well of the nMOS from the common-grounded P-substrate, and the DNW is connected to the highest voltage level (0V). Additionally, because the gate-oxide of low-voltage devices is thinner, each two adjacent nodes of devices do not exceed 1×VDD, which solves the gate-oxide reliability issue. Chapter 3 involves various measurements on the proposed circuits, including the analysis of tolerance and long-term reliability under both room temperature and harsh environmental conditions, to verify that it can effectively protect internal circuits. Chapter 4 summarizes that this paper proposes a high-voltage-tolerant ESD clamp circuit and also optimizes the area and conduction efficiency, presenting two different circuits. In the experimental results, the proposed ESD clamp circuit can effectively solve the electrostatic discharge problem for power pin of negative voltage without affecting the normal operation.