應用於輸出級驅動電路之靜電放電防護設計

Abstract

隨著製程演進，晶片微縮，靜電放電(ESD)容易造成晶片內部的電子元件遭受到不可逆之破壞，而所有的微電子產品必須符合此可靠度的規範。因此，靜電放電防護的可靠度議題必須被探討。 在積體電路的應用上，本論文設計了幾種新型的靜電放電防護元件，此元件在 0.18um 1.8V/3.3V CMOS製程下實現。透過實驗分析的結果，防護元件可以承受較大的訊號擺幅和能夠耐受 2kV 的人體放電模式之靜電放電測試。 為了驗證靜電放電防護元件在實際電路上的效能，本論文使用堆疊元件的輸出級驅動器並搭配嵌入式矽控整流器（Embedded SCR）。一種新型的靜電放電防護設計被提出來，為了改善其靜電放電的防護能力。此電路在 0.18um 1.8V/3.3VCMOS製程下實現。本論文所提出的防護設計經實際驗證，在不影響電路正常操作的情況下，有效改善其靜電放電的防護能力，證明所提出的設計可以改善靜電放電防護的能力。

關鍵字：靜電放電，輸出驅動器，矽控整流器

With the continuous evolution of semiconductor integrated circuits (ICs) process, electrostatic discharge (ESD) events are likely to cause internal electronic components of the wafer suffered irreversible damage. All microelectronic products must meet the reliability specifications. Therefore, ESD must be taken into consideration. In the application of integrated circuit, several novel ESD protection devices are designed in this work. By designing the structure, this work has been fabricated in 0.18-μm 1.8V/3.3V CMOS process. In the experimental results, this design can achieve large swing tolerance and endure 2kV human-body-model (HBM) test. In order to verify the protection ability of ESD protection device on the circuits, a novel design of stacked-device output driver with embedded silicon-controlled rectifier (SCR) is proposed to improve the ESD robustness. This work has been fabricated in 0.18-um 1.8V/3.3V CMOS process. Besides, the transient behaviors of the proposed design during normal operation are not degraded. Therefore, the proposed design can be used to improve the ESD robustness of stacked-device output driver.

Keywords: electrostatic discharge (ESD), output driver, silicon-controlled rectifier (SCR).