氧化鉿鋯材料系統之鐵電工程以邁向新興記憶體與邏輯應用
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2022
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鐵電氧化鉿鋯之鐵電工程為本論文主題，主要研究於記憶體及邏輯元件應用。記憶體應用方面，將討論鐵電場效應電晶體（FeFETs）可改善方向及面臨的問題，包括記憶體密度的挑戰、電荷俘獲和去極化效應以及wake-up效應。此外於電荷增加(charge boost)的發生機制中，將在反鐵電系統上採取有別一般理論的解釋方式，並提出雙向無電滯之方案。在第二章中，將使用反鐵電-正鐵電-電晶體進行兩位元的記憶體操作，其電晶體內含有四方晶向(tetragonal phase)及正交晶向(orthorhombic phase)的混合(反)鐵電向位。而四方晶向及正交晶向分別可以提供多峰矯頑場(coercive field)及殘餘極化(remnant polarization)的特性，進而得到較穩定的多位階操作及非揮發性記憶體能力。因此，利用反鐵電-正鐵電-電晶體在± 4 V的低電壓操作下，可得到多於10^5次的操作次數及在高溫環境下(65 ℃)的穩定資料儲存能力(>10^4 s)。
而為了提高記憶體資料保存穩定性的目的，在第3章節中將使用非等厚度的雙層鐵電氧化鉿鋯作為閘極堆疊結構。雙層鐵電氧化鉿鋯結構是利用一層氧化鋁的介電質材料作為隔層，分別將兩層不等厚度的氧化鉿鋯隔開，其上層及下層的鐵電氧化鉿鋯分別為5奈米及10奈米。這種設計是為了避免單斜晶向(monoclinic phase)在較厚的氧化鉿鋯中產生，以維持鐵電極化特性。此外，上層及下層的矯頑場不同，使得每一位階更加穩定及獨立，可以有效降低讀取時的錯誤率，且與單層鐵電氧化鉿鋯的閘極設計相比，可改善600倍的錯誤率。因此，雙層鐵電氧化鉿鋯作為非揮發性記憶體的多階單元並進行2位元可靠度測試時，可得到>10^5次的循環操作及>10^4秒的資料保存能力。
此外, 鐵電電晶體與三維結構技術的結合，例如:鰭式電晶體及閘極環繞電晶體，使得記憶體元件的尺寸能持續微縮至奈米等級，以增加單位面積下的記憶體單元，持續達到密度提升的目標。在第四章中，將三維的閘極環繞奈米片鐵電電晶體結構，並搭配雙層鐵電堆疊技術以作為高密度嵌入式非揮發性記憶體。而本章節中使用氮化鈦及氧化鋁兩種不同的隔層材料，其分別可對於操作電壓及記憶窗大小進行優化及改善。然而，奈米片的轉角結構使得極化方向互相抵消，產生較弱的極化區域-死區(dead zone)。而使用雙層氧化鉿鋯，外層的氧化鉿鋯有較大的曲率半徑，這可以減緩轉角效應。因此選擇TiN隔層的雙層鐵電氧化鉿鋯，可在± 3.5 V的操作電壓下，產生1.3 V的記憶窗、>10^11次卓越的操作能力及>2×10^4秒的資料保存能力。
然而，鐵電電晶體1T架構中存在寫入後讀取(read-after-write)之資料保存流失(retention loss)問題，鐵電電晶體在給予正極性的寫入電壓後，造成電荷被捕獲且殘留在氧化層與半導體層的介面，此捕獲電荷會抵消鐵電的電偶子產生的極化反應，使得臨界電壓在「寫後讀」的不穩定，造成錯誤讀取。此外，當閘極氧化層減薄後，會產生更大的去極化場，導致鐵電極化的衰退，這必須依靠給予一個閘極偏壓去抵抗去極化場，以避免極化衰退。因此，第五章將探討n型鐵電電晶體的「寫後讀」行為，並利用-1.5 V的反向極性電壓協助電荷「去捕獲」，並同時調整基準電壓，以抵抗去極化場造成的鐵電極化衰退。
在第六章中，將嘗試使用電漿增強原子層沉積系統(plasma-enhanced atomic layer doposition)進行鐵電氧化鉿鋯的薄膜優化。研究發現，使用電漿的輔助可減少氧化鉿鋯內的氧空缺(oxygen vacancy)，並使晶相形成較多的鐵電相位，避免電壓操作時的氧空缺重新排列造成的極化喚醒過程，達到免喚醒(wake-up free)的鐵電薄膜元件。另外，其可使用300 ℃的退火溫度，即形成良好的鐵電特性，以達到後段製程(BEOL)的所需的熱預算要求。負電容(negative capacitance)效應的理論根據與起源於目前尚有爭論。在過去幾年中，Landua-Ginzburg-Devonshire理論(LGD theory)被用解釋負電容現象產生的表面電荷增加。在第七章中，將使用另一解釋方式，利用反向切換(reverse switching)的概念討論電荷提升，實驗中使用AFE和AFE-DE系統來驗證反向極化切換所產生的電荷提升將會與飽和極化及殘餘極化的差有重要關係。此外，當AFE電容進行雙極性操作，可同時得到雙極性電荷提升及沒有遲滯現象的結果，此實驗結論支持了本實驗室於之前論文發表之電晶體實驗結果。
In this thesis, the HfZrO2 (FE-HZO) based ferroelectric engineering will be investigated for emerging memory and logic applications. For the memory, the issues of ferroelectric field-effect transistors (FeFETs) will be discussed, including the challenge of memory density, charge trapping and depolarization effect, and wake-up effect. An alternative explanation for charge enhancement will be adopted on antiferroelectric (AFE) HZO, and provides a strategy for bidirectional nonhysteretic released charge (QD) scheme.In chapter 2, the hybrid tetragonal (t) phase and orthorhombic (o) phase of antiferroelectric-ferroelectric-FET (AFE-FE-FET) is used for 2-bit memory operation. The t-phase and o-phase contribute to multipeak coercive field (EC) and remnant polarization (Pr), respectively, which results in stable multi states and nonvolatile memory (NVM) characteristic. Therefore, a low program/erase voltage (|VP/E| = 4 V) is demonstrated by AFE-FE-FET with more than 10^5 endurance cycles and stable data retention (>10^4 s at 65 ℃). In order to increase stability of multibit storage, an asymmetrical thickness of double-HZO is proposed as the gate stack in chapter 3. A double-HZO FeFET is two HZO layers separated by a dielectric (DE) of Al2O3 to avoid monoclinic (m) phase formation, and the top and bottom HZO are 5-nm-thick and 10-nm-thick, respectively. Besides, the EC difference of the top and bottom HZO is beneficial to stabilize each individual state, which exhibits lower error rate (ER) and shows a 600X improvement compared to single-HZO. As the results, a 2-bit endurance with>10^5 cycles and data retention >10^4 are demonstrated as a multilevel cell (MLC) for high density NVM application. In addition, three-dimensional (3-D) FeFETs (FinFET and GAAFET) are able to scale down toward nanoscale devices for high memory cell. In chapter 4, a 3-D GAA nanosheet (NS) FeFET with stacked HZO is based on double-HZO for high-density embedded NVM (eNVM). Two interlayers of TiN or Al2O3 in the double-HZO exhibits low access voltage or memory window (MW) enhancement, respectively.However, the corner of nanosheet structure leads to dead zone due to polarization compensation. The double-HZO can mitigate the corner effect with increasing curvature radius of outer HZO. Therefore, the double-HZO GAA-FeFET with interlayer TiN can use low operation voltage of ± 3.5 V to achieve large MW = 1.3 V,>10^11 robust endurance cycles, and data retention of 2×10^4 s. On the other hands, the issue of read-after-write for FeFETs retention loss in one transistor (1T) architecture is revealed in recent publications. The charge trapping occurs after a positive write pulse (VP) with n-FeFET. Trapped charges are residual in interfacial layer (IL) compensating FE polarization and needs relaxation time (delay time) to de-trap, which results in unstable threshold voltage (VT) and error readout for read-after-write. In addition, the depolarization field increases with scale-down thickness of FE-HZO. A base gate voltage (Vbase) is necessary to overcome depolarization to avoid polarization degradation. Therefore, an n-type FeFET of read-after-write is going to be discussed in chapter 5. An opposite polarity pulse of -1.5 V for detrapping (OPD) with adjustable Vbase is used simultaneously to mitigate retention loss of read-after-write.In chapter 6, the plasma-enhanced atomic layer deposition (PE-ALD) is adopted for FE-HZO film optimization. The lower oxygen vacancy (VO) and higher o-phase ratio can be observed by using PE-ALD, which is beneficial for ferroelectric films to avoid wake-up effect due to redistribution of oxygen vacancies to achieve wake-up free. Additionally, it shows a great FE characteristic under low annealing temperature of 300 ℃, which is an advantage for back end of line (BEOL) processes to satisfy the thermal budget requirement.The origins of negative capacitance (NC) have numerous publications and are controversial. The Landau–Ginzburg–Devonshire (LGD) theory has been used to explain the charge boost in the past years. In chapter 7, the reverse polarization switching concept provides another explanation of reverse switching concept to reveal charge enhancement effect. AFE and AFE-DE systems are used for comparison to insight the important role of the saturation polarization (PS) and Pr difference. The QD enhancement is observed with bipolar AFE operation and no QD difference (ΔQD), which supports our previously experimental results of FET.
In this thesis, the HfZrO2 (FE-HZO) based ferroelectric engineering will be investigated for emerging memory and logic applications. For the memory, the issues of ferroelectric field-effect transistors (FeFETs) will be discussed, including the challenge of memory density, charge trapping and depolarization effect, and wake-up effect. An alternative explanation for charge enhancement will be adopted on antiferroelectric (AFE) HZO, and provides a strategy for bidirectional nonhysteretic released charge (QD) scheme.In chapter 2, the hybrid tetragonal (t) phase and orthorhombic (o) phase of antiferroelectric-ferroelectric-FET (AFE-FE-FET) is used for 2-bit memory operation. The t-phase and o-phase contribute to multipeak coercive field (EC) and remnant polarization (Pr), respectively, which results in stable multi states and nonvolatile memory (NVM) characteristic. Therefore, a low program/erase voltage (|VP/E| = 4 V) is demonstrated by AFE-FE-FET with more than 10^5 endurance cycles and stable data retention (>10^4 s at 65 ℃). In order to increase stability of multibit storage, an asymmetrical thickness of double-HZO is proposed as the gate stack in chapter 3. A double-HZO FeFET is two HZO layers separated by a dielectric (DE) of Al2O3 to avoid monoclinic (m) phase formation, and the top and bottom HZO are 5-nm-thick and 10-nm-thick, respectively. Besides, the EC difference of the top and bottom HZO is beneficial to stabilize each individual state, which exhibits lower error rate (ER) and shows a 600X improvement compared to single-HZO. As the results, a 2-bit endurance with>10^5 cycles and data retention >10^4 are demonstrated as a multilevel cell (MLC) for high density NVM application. In addition, three-dimensional (3-D) FeFETs (FinFET and GAAFET) are able to scale down toward nanoscale devices for high memory cell. In chapter 4, a 3-D GAA nanosheet (NS) FeFET with stacked HZO is based on double-HZO for high-density embedded NVM (eNVM). Two interlayers of TiN or Al2O3 in the double-HZO exhibits low access voltage or memory window (MW) enhancement, respectively.However, the corner of nanosheet structure leads to dead zone due to polarization compensation. The double-HZO can mitigate the corner effect with increasing curvature radius of outer HZO. Therefore, the double-HZO GAA-FeFET with interlayer TiN can use low operation voltage of ± 3.5 V to achieve large MW = 1.3 V,>10^11 robust endurance cycles, and data retention of 2×10^4 s. On the other hands, the issue of read-after-write for FeFETs retention loss in one transistor (1T) architecture is revealed in recent publications. The charge trapping occurs after a positive write pulse (VP) with n-FeFET. Trapped charges are residual in interfacial layer (IL) compensating FE polarization and needs relaxation time (delay time) to de-trap, which results in unstable threshold voltage (VT) and error readout for read-after-write. In addition, the depolarization field increases with scale-down thickness of FE-HZO. A base gate voltage (Vbase) is necessary to overcome depolarization to avoid polarization degradation. Therefore, an n-type FeFET of read-after-write is going to be discussed in chapter 5. An opposite polarity pulse of -1.5 V for detrapping (OPD) with adjustable Vbase is used simultaneously to mitigate retention loss of read-after-write.In chapter 6, the plasma-enhanced atomic layer deposition (PE-ALD) is adopted for FE-HZO film optimization. The lower oxygen vacancy (VO) and higher o-phase ratio can be observed by using PE-ALD, which is beneficial for ferroelectric films to avoid wake-up effect due to redistribution of oxygen vacancies to achieve wake-up free. Additionally, it shows a great FE characteristic under low annealing temperature of 300 ℃, which is an advantage for back end of line (BEOL) processes to satisfy the thermal budget requirement.The origins of negative capacitance (NC) have numerous publications and are controversial. The Landau–Ginzburg–Devonshire (LGD) theory has been used to explain the charge boost in the past years. In chapter 7, the reverse polarization switching concept provides another explanation of reverse switching concept to reveal charge enhancement effect. AFE and AFE-DE systems are used for comparison to insight the important role of the saturation polarization (PS) and Pr difference. The QD enhancement is observed with bipolar AFE operation and no QD difference (ΔQD), which supports our previously experimental results of FET.
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(反)鐵電材料, 氧化鉿鋯, 非揮發性記憶體, 多位元記憶體, 新穎記憶體, 閘極環繞式電晶體, 電漿增強型原子層沉積, 後段製程, 免喚醒, 負電容效應, 電荷增加, 反向切換, (anti)ferroelectric materials, HfZrO2, nonvolatile memory, multibit memory, emerging memory, gate-all-around (GAA) FET, plasma-enhanced atomic layer deposition (PEALD), back end of line (BEOL), wake-up free, negative capacitance (NC) effect, charge enhancement, reverse switching