使用AB類/AB類開關運算放大器技術之0.7伏低功率低失真多位元三角積分調變器

Abstract

積體電路隨著製程技術的進步，已進入奈米的世界。然而在類比電路的設計與實現上卻沒有明顯受益，肇因於臨界電壓並未顯著減少，這對類比電路的設計是一大考驗。特別是低電壓電路要維持與一般電壓相同之效能是一項很大的挑戰。三角積分調變器對於類比電路元件的非理想特性不敏感，常運用於高解析度之電路，再結合超取樣技術、切換式運算放大器技術及雙取樣技術，可提升電路的性能。

本論文提出在供應電壓為0.7V的操作下，適用於音頻範圍之三階多位元低通三角積分調變器，使用TSMC標準0.18微米製程下完成兩個電路，一為改良型三階低失真三角積分調變器，另一個為具數位加強的三階低失真三角積分調變器。操作於25 KHz的頻寬，取樣頻率為4 MHz，個別的最大SNDR各為79.94 dB和80.14 dB，功率消耗為0.8897 mW和0.566 mW。

Though CMOS designing technology has had great improvements, analog circuit designing hasn’t gained much benefit due to the inconspicuous decrease of the threshold-voltage. This is a big problem for analog circuit designing, especially for low-voltage circuit designs, trying to maintain high performance under low voltages. Delta-Sigma Modulators have low sensitivity on non-ideal characteristics of analog circuits, so they’re usually designed for high-resolution systems. For high performance, oversampling, switched-OPAMP, and double-sampling techniques are applied.

This thesis presents a 0.7V third-order multi-bit low-pass delta-sigma modulator. We realize two modulators by TSMC 0.18um CMOS standard process: modified and digitally enhanced third-order low-distortion delta-sigma modulator. Both operate under 25KHz bandwidth and 4MHz sampling frequency, with 79.94 dB and 80.14dB SNDR. Total power dissipation are 0.8897 mW and 0.566 mW respectively.