28 GHz 向量合成式相移器與低雜訊放大器設計

Abstract

隨著第五代行動通訊(5th Generation Mobile Networks, 5G)帶動高速通訊的發展，資料傳輸需要更寬的頻寬來滿足大量傳輸需求，傳輸頻段必須往更高頻段移動，因此高頻訊號先天路徑損耗較大的問題變成必須克服的難題，本論文主要研究毫米波相位陣列系統之接收端電路設計，利用波束成形(Beamforming)技術來解決高頻傳輸路徑損耗過大問題。 第一顆電路介紹28GHz向量合成式相移器，電路採用0.18-μm 1P6M CMOS process實現，正交相位產生器使用正交耦合器和Marchand Balun組成。直流功率消耗為15.31 mW。整體晶片面積0.925 mm × 0.560 mm，操作頻率為26GHz至32GHz。在28GHz頻率上，插入損耗在9.8dB到19.5dB之間、RMS相位誤差為8.3°、RMS振幅誤差為3.8 dB。量測結果相位誤差較不理想，推測是耦合器與balun之間阻抗不連續造成。 第二顆電路介紹28GHz向量合成式相移器，旨在修正前一顆電路之正交相位產生器相位失準，在耦合器與balun之間加入匹配電感，使其阻抗連續。直流功率消耗為15.31 mW。整體晶片面積為0.925 mm × 0.555 mm，操作頻率為26GHz至32GHz。在28GHz頻率上，插入損耗在10.8dB到11.3dB之間，輸入反射係數為 -21.3 dB、輸出反射係數為 -8.4 dB、均方根相位誤差為0.64°、均方根振幅誤差為0.12 dB。 第三顆電路將介紹28GHz低雜訊放大器，為兩級串接疊接組態，本設計考量疊接組態增益以及雜訊指數，利用匹配電感使疊接組態之雜訊指數降低增益提高，並使用源極退化電感，以同時達到雜訊匹配以及共軛匹配。使用0.18-μm 1P6M CMOS process實現，供應電壓為2.4V，消耗功率為10.58 mW。整體晶片面積為0.650mm × 0.585 mm，量測結果增益在26.3 GHz 時有最大值15.7 dB，雜訊指數在28.5 GHz 的時候有最小值5.98 dB。線性度之量測結果，在量測頻率為27 GHz 時OP1dB為-1.9 dBm，在頻率28 GHz 時OP1dB為-1.7 dBm。With the development of high-speed communication and the fifth-generation mobile communication, data transmission requires a wider bandwidth to meet a large number of data transmission, transmission frequency must move to a higher frequency to obtain wide bandwidth requirements. Therefore, the high intrinsic path loss of these frequency bands becomes a design challenge. This paper studies the phase shifter design of millimeter-wave phased-array system used in beamforming systems. The first circuit is a 28GHz Vector Sum Phase Shifter fabricated in 0.18-μm 1P6M CMOS process. The quadrature-phase generator consisted of a quadrature coupler and Marchand Balun. The biggest dc consumption is 15.31mW. The chip area is 0.925 mm × 0.560 mm. The operation frequency is from 26GHz to 32GHz. At 28 GHz, the insertion loss is between 9.8dB to 19.5dB. The root mean square (RMS) phase error is 8.3°, and the RMS amplitude error is 3.8 dB. The measurement result did not fit the simulation well. We presumed that the impedance between coupler and balun did not match and it may influence the coupler’s phase difference and amplitude imbalance. The second circuit is a 28GHz Vector Sum Phase Shifter. In this design, our main goal is to fix the previous one’s phase difference of the quadrature generator. We series an inductor between coupler and balun to achieve conjugate matching. The biggest dc consumption is 15.31mW. The chip area is 0.925 mm × 0.560 mm. The operation frequency is from 26GHz to 32GHz. At 28 GHz, the insertion loss is between 10.8dB to 11.3dB. The input and output return loss is 21.3 and 8.4 dB, respectively. The root mean square (RMS) phase error is 0.64°, and the RMS amplitude error is 0.12 dB。 The third circuit is a 28GHz Low Noise Amplifier, which utilized two-stage cascode topology. This design mainly focuses on the gain and noise figure of the circuit. Using the source degeneration inductors, this can achieve a noise match and conjugate match simultaneously. This circuit was fabricated in 0.18-μm 1P6M CMOS process. The supply voltage is 2.4V. DC consumption is 10.58 mW. The chip area is 0.650mm × 0.585 mm. The measured peak gain is 15.7 dB at 26 GHz, and the measured noise figure is better than 5.9 dB at 28.5 GHz. The measured OP1dB is -1.9 dBm at 27 GHz, and -1.7 dBm at 28 GHz OP1dB, respectively.