多模式AES之小面積超大型積體電路設計

Abstract

進階加密標準(Advanced Encryption Standard, AES)在現場可程式邏輯閘陣列(field-programmable gate array，FPGA)與特殊用途積體電路(application-specific integrated circuit，ASIC) 的硬體實作已經被廣泛地討論，近幾年則朝向小面積硬體架構的議題做研究。 本實驗室在FPGA板子上所做的研究已經有相當豐碩的成果，但尚未實現成超大型積體電路(Very-large-scale integration，VLSI)。因此，本論文目標將改善本實驗室開發的AES硬體架構後，並架設工作站透過cell-based數位積體電路設計流程實現AES加解密晶片。 首先，本研究提出不使用記憶體的8-bit資料線完成128-bit AES硬體電路，進而發展出一個多模式小面積的架構。接著，本實驗室利用國家晶片研究中心(CIC)提供的工具，建立一套完整的數位積體電路設計環境。最後，透過標準元件設計流程(Cell-based design flow)來完成晶片製作，使其下線。

Advance Encryption Standard (AES) hardware implementation in FPGA and ASIC has been intensely discussed . In recent years , many researchers start to study low-area hardware architecture of AES . However, our team had many designs and scored great successes in FPGA , but we did not implement in very-large-scale integration(VLSI) yet before this paper was finished . Therefore, this paper dedicated to improve the hardware architecture of AES and set up IC design server , then through cell-based design flow to implement the AES chip. First, this paper presents an 8-bit data bus architecture of 128-bit AES without memory cells and propose a muti-mode low-area architecture of AES . Second, we use the EDA tools provided by the National Chip Implementation Center(CIC) to set up the development environment for VLSI design. Finally, we completed our first chip by following cell-based design flow , and taped out .