28 GHz鏡像訊號抑制接收機設計

Abstract

隨著毫米波頻段的發展，在毫米波射頻收發器中，低雜訊放大器及混頻器為射頻收發機的重要的元件。由於近年來互補式金氧半導體製程(CMOS)的發展愈趨前瞻，近年來一些射頻電路整合成的射頻模組也逐漸出現在市場上，因此本論文將使用TSMC 180nm CMOS製程，計實現28 GHz鏡像抑制接收器模組。第一個電路為28 GHz低雜訊放大器，使用串接兩極疊接組態結構，透過在疊接組態中加入匹配電感對雜訊進行抑制。當供應電壓Vdd為2.4 V，Vg1、Vg2分別為0.8 V、2 V時，量測在27.2 GHz有最大增益14.7 dB，雜訊指數在26 ~ 34 GHz雜訊指數小於6 dB，OP1dB約為-7.25 dBm，電路直流功率消耗約為10.87mW，整體晶片面積佈局為615 μm × 410 μm。第二個電路為28 GHz鏡像抑制混頻器，為一降頻器，射頻訊號由RF端進入後透過威爾金森功率合成器(Wilkinson Power Combiner)將訊號分配到I/Q混頻器中，LO端則是用耦合器和馬相巴倫構成的四相位產生器將差90度的正交的差動訊號輸入到I/Q混頻器中，IF端是以二階多相位濾波器(Poly Phase Filter)將輸出的四相位訊號合併成差動訊號。在LO驅動功率為3 dBm時，電晶體閘極偏壓在0.6V時，頻帶約為25 ~ 31 GHz，轉換增益(Conversion Loss)約為-20.48 dB，鏡像拒斥比在RF頻率28 GHz時為-47.18 dB，OP1dB約為-17.33 dBm，LO對RF、LO對IF隔離度皆小於-50 dB，電路直流功率消耗約為0 mW，整體晶片面積佈局為800 μm × 700 μm。第三個電路為28 GHz鏡像抑制接收器，由上述介紹的兩電路組成，由第一極的低雜訊放大器抑制雜訊並放大接收到的訊號，再由第二極的鏡像抑制混頻器做降頻和鏡像訊號抑制。當混頻器閘極電壓為0.6V、LO驅動功率供給3 dBm時，在頻率為28 GHz有最大的轉換增益約為-6.4 dB，RF頻寬鏡像拒斥比在20 GHz ~ 28 GHz小於-40 dB，IF頻寬鏡像拒斥比在在3 GHz ~ 5 GHz小於-40 dB，當LO頻率固定在25 GHz、RF頻率固定在28 GHz，LO驅動功率為3 dBm， OP1dB約為-27.15 dBm，LO到IF還是LO到RF的隔離度都有在-50 dB以下，直流功率消耗約為19.6 mW，整體晶片面積佈局為1200 μm × 700 μm。With the development of the millimeter-wave frequency band, low-noise amplifiers and mixers are important components in millimeter-wave RF transceivers. Due to the advancement of the complementary metal oxide semiconductor process (CMOS), some RF modules integrated with RF circuits have gradually appeared in the market in recent years. Therefore, this paper will use the TSMC 180nm CMOS process to achieve 28 GHz image rejection receiver module.The first circuit is a 28 GHz low-noise amplifier, which is composed of a two-stage cascode structure. Noise suppression is achieved by adding matched inductors to the cascode structure. When the supply voltage Vdd is 2.4 V, and Vg1 and Vg2 are 0.8 V and 2 V, respectively, the maximum gain is 14.7 dB at 27.2 GHz, and the noise figure is less than 6 dB at 26 ~ 34 GHz. The output power 1-dB gain compression point is about -7.25 dBm, the circuit DC power consumption is about 10.87mW, and the overall chip layout area is 615μm × 410μm.The second circuit is a 28 GHz image rejection mixer, which is a down-converter. The RF signal enters from the RF end than the signal distributes to the mixer of the I/Q path through the Wilkinson Power Combiner. At the LO end we use a four-phase generator composed of a coupler and two Marchand Blaun baluns to create the quadrature differential signal with a difference of 90 degrees into the I/Q mixer, and at the IF end a second-order polyphase filter(Poly Phase Filter) is utilized to combines the output four-phase signal into a differential signal. When the LO drive power is fixed at 3 dBm and the transistor gate bias is 0.6V, the conversion gain (Conversion Loss) is about -20.48 dB at 25 ~ 31 GHz, and when the RF frequency is 28 GHz, the image rejection ratio is -47.18 dB, the output power 1-dB gain compression point is about -17.33 dBm, RF to LO and RF to IF isolation are less than -50 dB, the circuit DC power consumption is about 0 mW, and the overall die layout area is 800 μm × 700 μm.The third circuit is a 28 GHz image-reject receiver, which consists of the two circuits described above. The first stage is a low-noise amplifier that suppresses noise and amplifies the received signal, and the second stage is an image-reject mixer to convert the received signal and suppress image signals. When the gate voltage of the mixer is 0.6V and the LO driving power is fixed at 3 dBm, the conversion gain is about -6.4 dB at 28 GHz, and the image rejection ratio is less than -40 dB at 20 GHz to 28 GHz.IF bandwidth image rejection ratio is less than -40 dB at 3 GHz to 5 GHz, when the LO frequency is fixed at 25 GHz, the RF frequency is fixed at 28 GHz, the LO drive power is 3 dBm, and the output power 1-dB gain compression point the OP1dB is about -27.15 dBm, the isolation from LO to IF or LO to RF is below -50 dB, the DC power consumption is about 19.6 mW, and the overall chip layout area is 1200 μm × 700 μm.