Design and analysis of a 77.3% locking-range divide-by-4 frequency divider
| dc.contributor | 國立臺灣師範大學應用電子科技學系 | zh_tw |
| dc.contributor.author | Yen-Hung Kuo | en_US |
| dc.contributor.author | Jeng-Han Tsai | en_US |
| dc.contributor.author | Hong-Yeh Chang | en_US |
| dc.contributor.author | Tian-Wei Huang | en_US |
| dc.date.accessioned | 2014-10-30T09:28:43Z | |
| dc.date.available | 2014-10-30T09:28:43Z | |
| dc.date.issued | 2011-10-01 | zh_TW |
| dc.description.abstract | A cascoded frequency divider (FD) with division number of 4 and ultra-wide locking range is presented in this paper. The proposed FD consists of a divide-by-2 (D2) injection-locked frequency divider (ILFD) core and a D2 source-injection current mode logic (SICML) divider. After the cascoded integration of ILFD and SICML, the removal of transconductance and buffer stages can lower the dc power consumption and widen the locking range. The proposed FD is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. Compared to the previously reported ILFDs, the proposed circuit achieves the widest locking range without employing extra tuning mechanism. | en_US |
| dc.description.uri | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5970079 | zh_TW |
| dc.identifier | ntnulib_tp_E0611_01_004 | zh_TW |
| dc.identifier.issn | 0018-9480 | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32240 | |
| dc.language | en | zh_TW |
| dc.publisher | IEEE Microwave Theory and Techniques Society | en_US |
| dc.relation | IEEE Transactions on Microwave Theory and Techniques, 59(10), 2477-2485. | en_US |
| dc.subject.other | CMOS | en_US |
| dc.subject.other | current mode logic (CML) latch | en_US |
| dc.subject.other | divide-by-4 (D4) | en_US |
| dc.subject.other | injection-locked frequency divider (ILFD) | en_US |
| dc.subject.other | monolithic microwave integrated circuit (MMIC) | en_US |
| dc.subject.other | phase-locked loop (PLL) | en_US |
| dc.subject.other | wide locking range | en_US |
| dc.title | Design and analysis of a 77.3% locking-range divide-by-4 frequency divider | en_US |