An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process
| dc.contributor | 國立臺灣師範大學應用電子科技學系 | zh_tw |
| dc.contributor.author | Yu-Hsuan Lin | en_US |
| dc.contributor.author | Jeng-Han Tsai | en_US |
| dc.contributor.author | Yen-Hung Kuo | en_US |
| dc.contributor.author | Tian-Wei Huang | en_US |
| dc.date.accessioned | 2014-10-30T09:28:45Z | |
| dc.date.available | 2014-10-30T09:28:45Z | |
| dc.date.issued | 2011-12-08 | zh_TW |
| dc.description.abstract | A 24 GHz 29.8 mW Phase-lock-loop using 0.18 μm CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm2 without off-chip loop filter. | en_US |
| dc.description.uri | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6174079 | zh_TW |
| dc.identifier | ntnulib_tp_E0611_02_002 | zh_TW |
| dc.identifier.uri | http://rportal.lib.ntnu.edu.tw/handle/20.500.12235/32261 | |
| dc.language | en | zh_TW |
| dc.relation | Asia-Pacific Microwave Conference,Melbourne, VIC,pp1630 - 1633 . (EI, NSC 100-2219-E-002-011 and NSC 100-2221-E-003-027).� | en_US |
| dc.subject.other | CMOS | en_US |
| dc.subject.other | Phase-Lock-Loop (PLL) | en_US |
| dc.subject.other | VCO | en_US |
| dc.subject.other | Injection-Locked Frequency Divider(ILFD). | en_US |
| dc.title | An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process | en_US |