X頻帶接收器前端電路與E頻帶低雜訊放大器設計與實現

Abstract

本論文主要針對X頻帶衛星通訊與E頻帶無線通訊之訊射頻前端電路的設計與實現，包含低雜訊放大器與混頻器，晶片製作透過國家晶片中心提供的標準TSMC CMOS 90 nm與180 nm製程，內容分為三個部分，第一個部分為介紹X頻帶與E頻帶的研究背景，第二部分為所有電路設計、模擬與量測，第三部分為結論。 本論文將介紹三個電路，依序為X頻帶低雜訊放大器、E頻帶低雜訊放大器、X頻帶混頻器，分別在第二章、第三章與第四章。第二章實現了X頻帶低雜訊放大器，使用兩級共源極組態串接的方式，並採用變壓器匹配的方式能在低功率消耗、低雜訊與小面積下維持不錯的增益表現，量測在11 GHz下有小訊號增益13.4 dB，雜訊指數3.41 dB。在供應電壓1.0 V下整體功率消耗為4.8mW。晶片面積為0.44 〖mm〗^2。 第三章實現了E頻帶低雜訊放大器，採用三級串接組態的架構，第一級為共源極組態，第二級與第三級都是採用疊接組態，並且延續前一章節所使用的變壓器匹配方式減少晶片使用的面積，量測結果最大訊號增益在67 GHz有21 dB，雜訊指數在67.5 GHz為8.8 dB，在共源極組態與疊接組態供應電壓分別為1.2 V與2.4 V下的整體功率消耗為15.84 mW。晶片面積為0.338 〖mm〗^2。 第四章實現了X頻帶環形混頻器，採用弱反轉區的偏壓方式，混頻器可以操作在低LO功率以及低直流功率消耗，並在輸出IF端使用轉阻緩衝放大器提供足夠的轉換增益，量測轉換增益為0.5 ± 1.5 dB在9 ~ 15 GHz。LO驅動功率為-12 ~ -5 dBm，整體供應電壓為1.0 V，功率消耗為2 mW。晶片面積為0.295 〖mm〗^2。The thesis is to develop design techniques of RF receiver front-end integrated circuits for X-band satellite communication system and E-band wireless communication system, including low noise amplifier (LNA) and mixer. The circuits are designed and fabricated on TSMC 180 nm 1P6M CMOS process and 90nm 1P9M CMOS process. The thesis is divided into three parts. The first part is the introduction of the X-band and E-band applications. The second part is total circuit design, simulation, and measurement results. Finally, a brief conclusion is given in the last part. An X-band low noise amplifier, an E-band low noise amplifier, and an X-band ring mixer are presented in chapter 2, chapter 3, and chapter 4, respectively. Chapter 2 aims to develop an X-band low noise amplifier. A general overview of LNA design is given. The LNA uses two-stage common source configuration with transformer matching networks. It can achieve low power, low noise, and compact size while maintaining reasonable gain performance. The measured small signal gain and noise figure are 13.4 dB and 3.41 dB at 11GHz, respectively. The measured output 1-dB compression point (OP_1dB) is -2 dBm at 11 GHz. The total power consumption is 4.8 mW from 1.0 V supply voltage. The chip size is 0.44〖 mm〗^2. The E-band low noise amplifier is presented on chapter 3. The LNA utilizes three-stage cascade configuration. The first stage is common source configuration for low noise consideration. The cascode configuration is selected for second and third stages to achieve high gain at E-band. The simulated maximum small signal gain is 21 dB at 67 GHz with total power consumption of 15.84 mW. The 3-dB bandwidth is 66 to 70 GHz. The noise figure is 8.8 dB at 67.5 GHz. The measured output 1-dB compression point (OP_1dB) is -8.2 dBm at 67 GHz. The chip size is 0.338 mm^2. The last circuit in chapter 4 is an X-band down conversion ring mixer. By using a weak inversion biasing technique, the ring mixer can operate at a low LO drive power and low dc power consumption. In addition, an IF buffer amplifier is utilized to provide good conversion gain for the mixer. The measured flat conversion gain is 0.5 ± 1.5 dB from 9 to 15 GHz. The LO drive power is -8 dBm. The measured output 1-dB compression point (OP_1dB) is -14.15 dBm. The total power consumption is 2 mW of 1.0 supply voltage. The chip size is 0.295 mm^2.