3.5 GHz向量合成式相移器與38 GHz鏡像抑制降頻器設計

Abstract

本論文主要研究領域為應用於第五代行動通訊之相移器與降頻混頻器。目前第五代行動通訊開放6 GHz以下頻段（Sub-6 GHz）及毫米波頻段（mmWave），主要使用頻段為3.5 GHz。當需要高速傳輸時，會轉換至毫米波頻段（mmWave）目前第一步開放28 GHz下一階段將開放38 GHz，目前主要往3.5 GHz以及38 GHz這兩個頻段發展。為了做出高精準度之相移器，採用向量合成式向移器，第二章將簡單介紹各類相移器及項移器主要設計參數，第三章與第四章將對向量合成式相移器進行分析，接著說明兩顆向量合成式之設計與實現。第一顆相移器，使用SiGe18 BiCMOS製作，四相位產生器使用多相位濾波器(PPF)實現。操作頻率在3.5GHz時，插入損耗平均值為-8.89dB，IP1dB為0dBm，功率消耗為18.94mW，相位誤差均方根為0.099度以及振幅誤差均方根值為0.113dB。 第二顆晶片為第一顆晶片的改良，使用TSMC 65nm COMS，能進一步降低插入損耗與功率消耗，針對3.5 GHz做輸出匹配以提高增益並刪去不必要之電晶體。當操作頻率在3.5 GHz時，插入損耗平均值為-3.51dB，IP1dB為0dBm，功率消耗為8mW，相位誤差均方根為0.3612度以及振幅誤差均方根值為0.117dB。 本論文最後一章介紹第三個電路，採用TSMC 65nm COMS製程設計之鏡像抑制降頻器，LO四相位產生器使用傳輸線做為補償，以及對90度耦合器挖地，可以讓90度耦合器的耦合量增加並改善IQ訊號不平衡的問題，IF端四相位合成採用多相位濾波器合成，由於多相位濾波器損耗較大，因此在IF端加上緩衝放大器來提升整體增益、在LO驅動功率為3 dBm，IF頻率為4.3 GHz時，在36 GHz至40 GHz鏡像抑制效果大於35 dB，轉換增益為-5±1 dB。The main research field of this thesis is based on phase shifter and Image Rejection Down -Comverter. From telecommunication to big data, higher frequency spectrum is needed for the large amount of data. Therefore, in order to satisfy tremendous data transmission,the fifth generation wireless communication system has been proposed and populated. The three circuits in this paper are applied at 3.5 GHz and 38 GHz, which is the potential spectrum in 5G systems. In the first half of this thesis, we introduce different types of phase shifter, and analyze switch type phase shifter used in this thesis. Then, we discuss the design and implementation on two circuits, phase shifters. The first circuit is vector sum phase shifter, using TSMC SiGe18 BiCMOS. Quadrature signal generator used polyphaser filter circuit and vector adder use Gilbert cell circuit. The frequency operated at 3.5 GHz has 0.099° RMS phase error and 0.113 dB RMS amplitude error. Insertion loss is -8.89dB. Power consumption is 18.94 mW. The second circuit is to improve the first circuit. In order to increase gain and reduce power consumption and reduce area, the circuit is fabricated using TSMC 65nm COMS. Quadrature signal generator using polyphaser filter circuit and vector adder use Gilbert cell circuit. The frequency operated at 3.5 GHz has 0.361° RMS phase error and 0.117 dB RMS amplitude error. Insertion loss is -3.51dB. Power consumption is 8 mW. The rest of this thesis, the third and also the final chip circuit is introduced. A high image rejection down-converter mixer designed at 38GHz. The conversion gain is -5±1 dB at LO power of 3 dBm and lower than 40 dB image rejection when the mixer ranged from 36 GHz to 40 GHz. Power consumption is 8 mW.