Sub-100nm及更先進製程之退火負載效應

Abstract

最近十五年以來，快速熱退火製程時的圖案效應已經廣泛的被研究，可是這僅僅只能達到現在的元件生產要求，這類的RTA負載效應的研究與評估對於未來更先進的製程都是有相當難度的。隨著元件尺寸縮小，我們需要選擇新的退火技術來符合下個世代的工業科技。先進的退火技術，例如 Flash Lamp 退火（FLA）與雷射退火 (Laser) 將提供改善摻雜濃度的活化程度並減少雜質擴散(Transient Enhance Diffusion, TED)以達到超淺接面需求，針對源極,汲極與閘極區域部分，更勝於尖峰快速熱退火（spike RTA）技術。此時間小於千分之一秒的退火技術，通常寄予希望的，來藉此符合先進的CMOS製程技術。短時間的區隔尖峰快速熱退火和時間小於千分之一秒的退火技術在溫度上升時，在表面及局部的溫度分部將有明顯的影響藉著局部的設計圖形，這將可以歸因於矽的本質熱傳導係數和較短的側面熱的擴散長度。除此之外，我們將模擬在有圖型負載效應下的元件電性。 於是我們得到一個最佳化的情況就是在Laser 與FLA 的退火條件下，poly space 的間隔為0.22微米時為最佳化條件。而且此退火之負載效應在對於NMOS元件更勝於PMOS元件。

Pattern effects of RTA (Rapid Thermal Process) have been extensively studied for the last 15 years, but have only recently attained focus in device production. The detection and the evaluation of RTA pattern effects are difficult to reach the requirement of deep sub-micro meter technology node or more. With the devices scaling down, the new annealing method is necessary for next generation technologies. For flash lamp annealing (FLA) and laser annealing of the advanced annealing techniques are not only improve dopant activation for source-drain and gate polysilicon regions, but also be retarded the effect of TED (transient enhance diffusion) to obtain ultra shallow junction, as compare with the spike rapid thermal annealing (sRTA) techniques. The sub-millisecond annealing is also expected to attain the demand of advanced CMOS technology. Due to the intrinsic thermal conductivity of Si and shorter lateral thermal diffusion length, the temperature of nearly local/surface will be highly influenced by the local laylout geometry for the short time interval spike RTA and sub-millisecond annealing techniques with temperature increasing. Besides, we also simulate the electrical characteristics by pattern loading effect and show the optimized poly space of 0.22 m for Flash and Laser annealing. NMOS is more sensitive to poly spaces loading effect than that of PMOS.