超薄氧化銦基電晶體製程

Abstract

由於電晶體的微縮持續發展，處理器核心速度提升為 Moore Law(摩爾定律)，但整體性能的系統與能量消耗問題仍存在瓶頸，記憶體與邏輯內核間數據流量大幅上升，造成功耗損失迫使處理器增加等待數據時間，為了解決此瓶頸利用3DIC(積層型三維積體電路)的異質整合來達成computing-in-memory(CIM)記憶體內運算，並且(Monolithic 3D；M3D) 單體3D有高密度的優勢。除了傳統半導體Poly-Si，氧化物半導體作為通道選擇，具有製程相容性，以免除磊晶高成本低產出缺點，並且氧化物半導體具有低溫製程的優勢，所以能應用在後段製程(BEOL-Back end of line)，此實驗成功濺鍍10nm In2O3(氧化銦) 材料作為通道於鐵電容整合打造出M3D垂直立體結構元件，且在BEOL製程的應用，並以量測結果證實閘極閾值電壓(ID-VG)成功繞出順時鐘的路徑轉換至逆時鐘的路徑，具有鐵電的特性。鐵電電場與極化，P-V量測結果，成功繞出PV-Loop鐵電遲滯曲線，證實In2O3與鐵電容整合的元件，具有鐵電的電容。另外為了改善In2O3通道材料，增加製程上熱預算的限制，成功濺鍍超薄2nm IWO(氧化銦摻鎢)於薄膜電晶體的元件，並有極好電流開關比達到>107 以及很高的載子遷移率10.64 cm2/V-s，IWO作為通道材料，未來應用於BEOL的M3D有很大的潛力，有望大幅提升未來元件的效能。Due to the continuous development of transistor miniaturization, the processor core speed has been increased by Moore's Law, but there is still a bottleneck in the overall performance of the system and the energy consumption problem. The data traffic between memory and logic cores has increased dramatically, which results in the loss of power consumption and forces the processor to increase the waiting time for data. Computing-in-memory (CIM) and Monolithic 3D (M3D) have the advantage of high density. In addition to the traditional semiconductor Poly-Si, oxide semiconductor as a channel choice, with process compatibility, to eliminate the epitaxial high cost and low yield shortcomings, and oxide semiconductor has the advantage of low-temperature process, so it can be applied in the back end of the line (BEOL-Back end of line), this experiment successfully sputtering 10nm In2O3 material as a channel in the ferroelectric capacitors. This experiment successfully sputtered 10nm In2O3 material as a channel in ferroelectric capacitor to create M3D vertical three-dimensional structure components, and applied in BEOL process, and the measurement results confirmed that the gate threshold voltage (ID-VG) was successfully converted from clockwise path to anticlockwise path, which has the characteristics of ferro-electric. Ferro-electric field and polarization, P-V measurement results, successfully winding the PV-Loop ferro-electric hysteresis curve, proving that the integration of In2O3 and ferroelectric capacitance of the component has the capacitance of ferro-electricity. In addition, in order to improve the In2O3 channel material and increase the limitation of thermal prediction in the process, we have successfully sputtered Ultra-thin 2nm IWO(In2O3 doped in W) on thin-film transistor components with excellent current-switching ratios up to>107 and a very high carrier mobility of 10.64 cm2/V-s. As a channel material, the future application of IWO for BEOL M3D has great potential, and is expected to significantly improve the performance of future components. Enhance the performance of future components