具應力梯度接觸蝕刻停止層與源、汲極晶格不匹配對N型奈米元件的影響

Abstract

本研究旨在分析具多重應力源結構之N型奈米電晶體，其元件結構尺寸對於元件應力分佈之性能及表現。該電晶體結構之多重應力源包括：1、晶格不匹配之源/汲極區域，以及2、在厚度方向上具應力梯度之接觸蝕刻停止層（CESL）。藉由本研究所提出之創新模擬法所得之分析結果證實，由具應力梯度之CESL結合矽碳源/汲極晶格不匹配引致應力源之先進應變工程技術，能夠精準預測真實電晶體通道區域之應力與應變分佈情形。為了探討CESL薄膜應力梯度對本研究之影響，本研究施予1.0 GPa拉伸內應力，在模擬分析時固定其厚度，並分別以多次沈積方式諸如1、2、4、8與12次，以逐層堆疊的方式進行數值收斂性分析；結果得知沈積次數愈多者將愈接近實際元件之應力分佈，且元件通道應力分佈將收斂於一定值。採用上述模擬方式對具 1.0 GPa t-CESL及源/汲極區域鑲埋1.65 %碳莫耳分率之矽碳合金之多重應力源結構，進行電晶體通道寬度調變模擬分析，其結果指出，多重應力源結構改善電晶體之效能將優於單一應力源結構，而隨著通道寬度越寬，通道應力趨於飽和，並且經由一階壓阻係數關係式，得知電晶體性能提升比例。 此外，考慮多重應力源結構對於鍺基板電晶體的性能表現，並藉由本論文使用之創新模擬方法，將具應力梯度之t-CESL結合鍺矽源/汲極晶格不匹配引致應力之多重應力源結構進行模擬分析。結果指出，越高的矽莫耳分率之鍺矽合金，對通道應力影響越大，並且隨著通道寬度的延伸，應力趨於飽和，最後由一階壓阻係數關係式，獲得鍺基板電晶體性能提升比例。Advanced strained engineering techniques, including embedding stressors from lattice mismatch in source and drain (S/D) regions and the contact etch stop layer (CESL), have been widely adopted in nano-scale transistors to enhance the device performances. In order to accurately estimate the stress impact from CESL, the influence of stress gradient along the film thickness direction of CESL induced from the process of film deposition needs to be taken into account. For this reason, an innovative simulation methodology for simulating the stress gradient behavior of CESL is proposed in this research. A validated vehicle of n-type MOSFET combined S/D SiC stressors with a 1.65% mole fraction of carbon and tensile CESL is used to analyze the stress contour distribution and performance of the foregoing device while the present estimated approach is performed. To create the stress gradient behavior of a CESL film in stress simulation of devices, a whole fixed CESL thickness is divided into several sub-layers and react each sub-layer from the bottom to the top step by step in the analysis. It should be noted that a tensile 1.0 GPa of CESL is utilized in the finite element analysis of stress simulation. According to the analytic results of a fixed CESL thickness divided by 1, 2, 4, 8, and 12 layers, a numerical convergence in stress magnitude of device channel is obtained. In order to observe the stress distribution of device in three-dimensional field, the research executes a parameter analysis in the channel width. The result shows that a wider channel results in a more obvious bending moment effect. It leads to an increased channel stress and hence an improved device. It is found that the channel stress would be saturated when the channel width is wider than 1µm. After extracting stress components of device channel, carrier mobility gain can be estimated via a first-order stress-piezoresistivity model.