應用於寬頻之靜電放電防護設計

Abstract

本論文提出了一種應用於寬頻積體電路之全晶片靜電放電防護設計，在0.18μm CMOS製程下，以矽控整流器元件搭配分散式電路的設計，並與既有二極體元件的設計相比較。 當內部電路的操作頻率上升，寄生電容造成的訊號損耗也益加嚴重，單級的靜電放電防護設計不再適用於高頻電路，為了維持原有的防護效果，本論文提出π型架構的設計，將單級的防護元件以小尺寸分散至兩級，藉由匹配元件的使用，來降低訊號通過時的損耗，傳統的π型架構設計使用的是二極體元件，本論文則是採用矽控整流器元件搭配π型架構，矽控整流器在單位面積下具有高的靜電放電耐受度，藉由二極體串的觸發，導通速度得以提升，並藉由電感的使用來達到良好的寬頻表現。 最後，將傳統二極體設計與本設計應用於K波段下的低雜訊放大器，透過電路的量測結果，驗證對電路的影響與實際的防護效果。

This thesis proposed a whole-chip electrostatic discharge (ESD) protection design for broadband circuits. In 0.18μm CMOS process, the silicon-controlled rectifier (SCR) is designed with distributed circuit in comparison with traditional design by diode. As the operating frequency of IC increases, the signal loss caused by ESD protection device is more severe. The ESD protection design with one stage is no longer suitable for high-frequency applications. π-model structure is proposed to solve this problem. The device is divided into two sections. Two parts are connected with an inductor. By the use of matching element, the signal loss is reduced. Traditional π-model structure is realized with diode. This thesis proposed a π-model design with SCR. SCR has great ESD robustness per unit area. With the trigger diodes, the turn-on efficiency of SCR can be improved. With the help of matching inductor, the broadband performance is maintained. Traditional design and proposed design are realized with K-band low-noise amplifier (LNA) to learn the protective effect.