Browsing by Author "Deng-Yao Shi"

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A Low-Voltage Fourth-Order Cascade Delta-Sigma Modulator in 0.18 um CMOS
(IEEE Circuits and Systems Society, 2010-09-01) Chien-Hung Kuo; Deng-Yao Shi; Kang-Shuo Chang
In this paper, a low-voltage fourth-order 2-2 cascade delta-sigma (ΔΣ) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the ΔΣ modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order ΔΣ modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented ΔΣ modulator is fabricated in a 0.18- μm 1P6M CMOS technology. The chip core area without PADs is 1.57 mm2 . The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance.
A Sixth-Order 4-2 SMASH CIFF Complex Bandpass Delta-Sigma Modulator with Delaying Digital Input Feedforward
(2010-06-02) Chien-Hung Kuo; Hung-Jing Lai; Deng-Yao Shi
In this paper, a sixth-order sturdy multi-stage noise shaping (SMASH) bandpass delta-sigma (ΔΣ) modulator with delaying digital input feedforward (DFF) structure is presented. The second-order ΔΣ modulator with cascade integrators and distributed feedforward (CIFF) is utilized in each stage to reduce the signal swing. Hence, the requirement of opamp and the power consumption of circuits can be reduced due to the suppression of the signal swing and the discarding of the digital cancellation filters. One pair of complex zeros is designed within signal bandwidth to effectively suppress the noise floor of the presented modulator. The sub-sampling technique is adopted to reduce the clock frequency and the requirement of opamp. Simulation results confirm the feasibility of the proposed SMASH CIFF bandpass ΔΣ modulator with delaying DFF structure. The proposed bandpass ΔΣ modulator compared to the single-loop AFF structure, the signal-to-noise plus distortion ratio (SNDR) could be increased by 12 dB, and the dynamic range (DR) could be extended by roughly 15 dB in a 200 kHz of signal bandwidth centered at 10.7 MHz.
應用於音頻之低功率高效能三角積分調變器設計與實現
(2011) 施登耀; Deng-Yao Shi
在現今製程技術不斷的進步下，積體電路設計已進入了奈米時代，此進步不但大大的降低了電路的面積，相對上電源供應電壓也大幅的下降。高效能、低功率的晶片陸續地推陳出新，以及人們對於產品輕薄短小和電池的長時效性要求，低功率積體電路技術發展有愈來愈急迫的需要。然而，電源電壓的下降，雖可有效地節省數位電路的消耗功率，但卻反而增加類比數位轉換電路設計的困難。在許多應用當中，類比數位轉換器(Analog-to-digital converter)佔著舉足輕重的角色，而有許多種架構可以來完成。三角積分調變器(Delta Sigma Modulator)對類比電路的非理想特性並不敏感，這些特性包含元件之間的不匹配、運算放大器的增益等等。然而這些特性恰巧對低功率電路來說尤其重要。三角積分調變器這項技術基本上非常適合用來實現高解析度、高準確度、及窄頻要求的類比數位轉換器，因此在儀器、音頻及通信上的應用已相當的普遍。在本論文中，提出了兩種新穎的架構並且實現，一是改良強健式多級雜訊頻移架構(Sturdy Multi-stage Noise Shaping, SMASH)，降低運算放大器對電壓增益的需求，並結合數位前饋架構(Digital feed-forward)，增加輸入動態範圍且降低失真；二為，三角積分調變器使用逐次逼近暫存式(Successive Approximation Register, SAR)類比數位轉換器，此架構可有效降低功率消耗和電路複雜度。兩架構實現所使用的製程技術分別為TSMC 90-nm 1P9M CMOS與TSMC 0.18-mm 1P6M CMOS；設計的供應電壓皆為1.2 V、頻寬為音頻應用的25 kHz；模擬結果分別達到的最大SNDR為63 dB與82 dB；電源功率消耗分別為813 mW與463 mW。