應用於音頻之低功率高效能三角積分調變器設計與實現

Abstract

在現今製程技術不斷的進步下，積體電路設計已進入了奈米時代，此進步不但大大的降低了電路的面積，相對上電源供應電壓也大幅的下降。高效能、低功率的晶片陸續地推陳出新，以及人們對於產品輕薄短小和電池的長時效性要求，低功率積體電路技術發展有愈來愈急迫的需要。然而，電源電壓的下降，雖可有效地節省數位電路的消耗功率，但卻反而增加類比數位轉換電路設計的困難。在許多應用當中，類比數位轉換器(Analog-to-digital converter)佔著舉足輕重的角色，而有許多種架構可以來完成。三角積分調變器(Delta Sigma Modulator)對類比電路的非理想特性並不敏感，這些特性包含元件之間的不匹配、運算放大器的增益等等。然而這些特性恰巧對低功率電路來說尤其重要。三角積分調變器這項技術基本上非常適合用來實現高解析度、高準確度、及窄頻要求的類比數位轉換器，因此在儀器、音頻及通信上的應用已相當的普遍。

在本論文中，提出了兩種新穎的架構並且實現，一是改良強健式多級雜訊頻移架構(Sturdy Multi-stage Noise Shaping, SMASH)，降低運算放大器對電壓增益的需求，並結合數位前饋架構(Digital feed-forward)，增加輸入動態範圍且降低失真；二為，三角積分調變器使用逐次逼近暫存式(Successive Approximation Register, SAR)類比數位轉換器，此架構可有效降低功率消耗和電路複雜度。兩架構實現所使用的製程技術分別為TSMC 90-nm 1P9M CMOS與TSMC 0.18-mm 1P6M CMOS；設計的供應電壓皆為1.2 V、頻寬為音頻應用的25 kHz；模擬結果分別達到的最大SNDR為63 dB與82 dB；電源功率消耗分別為813 mW與463 mW。The fabrication of integrated circuit has entered the nano-grade with the improvement of modern technology. This progress not only reduces the circuit area greatly, but also lowers the supply voltage significantly. Chips with high-performance and low-power have been proposed constantly today, the main demand of these chips nowadays is more power saving for portability. Hence, the low power technology has become a trend in modern integrated circuit designs. Although the decreasing of the supply voltage can effectively save power consumption of digital circuits, it also increases the difficulty of designing analog-to-digital converters (ADCs) circuits, which plays an important role in many applications. Fortunately, Delta-sigma modulators are insensitive to the imperfections of the analog components, including the mismatch between elements, the gain of OPAMPs, etc… which are of great influence to low-power chips. Therefore, they’re usually designed and applied for high-resolution systems such as instruments, audio devices, and communication devices.

In this thesis, we propose and construct two new structures. The first one is an improved Sturdy Multi-stage Noise Shaping (SMASH) structure. Here are three key-points of SMASH: (a) it reduces the gain requirement of the operational amplifier (OPAMP) (b) analogy modulator adopting the Digital feed-forward (DFF) path (c)input dynamic range larger than conventional DSM with the distortion of modulator reduced. The second structure is a  modulator using successive approximation register (SAR) ADC. This architecture reduces power consumption and simplifies circuit complexity. Two of the modulators are constructed in 90-nm 1P9M CMOS and 0.18-m 1P6M CMOS process technology, respectively. Both modulators process 25-KHz audio-band, with 63 dB and 82dB peak SNDR. Total power dissipations are 813 mW and 463 mW, respectively.