具 1-1 MASH 架構的雜訊移頻循序漸進式類比數位轉換器設計與實現

Abstract

本文提出一種具1-1多級雜訊移頻(Multistage Noise-Shaping, MASH)架構的雜訊移頻循序漸進式(Noise-Shaping Successive-Approximation Register, NS-SAR)類比數位轉換器(Analog-to-Digital Converter, ADC)。所提出的類比數位轉換器是一種混合型超取樣(Oversampling)類比數位轉換器結構，它結合了循序漸進式與三角積分(Delta-Sigma, ΔΣ)兩種類比數位轉換器的優點，可以在實現高解析度及大頻寬的同時並具有良好功耗效率。此三角積分調變器設計中的單級迴路使用具前饋求和的級聯積分器(Cascade of Integrators with Feed-Forward Summation, CIFF)架構，由於CIFF架構中積分器的路徑上不包含輸入訊號，迴路濾波器僅需處理調變過程中產生的量化誤差，因此迴路濾波器的輸出振幅很小，意味著可以放寬轉導放大器(Operational Transconductance Amplifier, OTA)設計上的迴轉率性能要求，也代表該架構的迴路濾波器適合用架構簡單且功耗低的基於反向器的轉導放大器來實現。此外，為了降低電路的複雜度，作者提出了一種無加法器的求和電路結構，它在不依賴額外電路的情況下實現了CIFF架構的輸入前饋求和功能和提取MASH架構的第一級量化誤差。所提出的電路使用TSMC 0.18-μm 1P6M標準CMOS製程技術所製造。不含PAD的晶片核心面積為0.084 mm2。在供應電壓1.4 V、取樣頻率4.0-MS/s、20 kHz及的頻寬下，實現了72.9 dB的訊號雜訊失真比(Signal-to-Noise and Distortion Ratio, SNDR)。此外，端看功率頻譜密度圖的斜率驗證了具有完整的二階雜訊移頻。This thesis presents a noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) with 1-1 multistage noise-shaping (MASH) structure. The proposed ADC is a hybrid oversampling ADC architecture that combines the advantages of both SAR and delta-sigma (ΔΣ) ADCs and can achieve high resolution and wide bandwidth with good power efficiency. The single stage topology in the ΔΣM design using cascade of integrators with feed-forward summation (CIFF) structure. Because the output signals of integrators in CIFF structure are not contain the input signal, which means that this loop filter process quantization error only, thus the output swing requirements of the loop filter will decrease, it means that the slew-rate requirement is not critical when we design the operational transconductance amplifier (OTA) in loop filter, so it is more suitable for inverter-based OTA. Besides, the author proposed an adder-free summing circuit architecture to reduce circuit complexity, which realizes the input feed-forward summing function of the CIFF structure and extracts the 1st quantization error of the MASH structure without relying on additional circuits.The prototype was fabricated using TSMC 0.18-μm 1P6M CMOS technology. The chip core area without PADs is 0.084 mm2. At 1.4 V supply, sampling rate of 4.0-MS/s, bandwidth of 20 kHz, the prototype achieves 72.9 dB SNDR. Besides, the slope of power spectral density (PSD) verifies the almost 2nd noise-shaping successfully.